This invention relates generally to power converters and, more specifically, relates to signal generation for power converters and use thereof.
This section is intended to provide a background or context to the invention disclosed below. The description herein may include concepts that could be pursued, but are not necessarily ones that have been previously conceived, implemented or described. Therefore, unless otherwise explicitly indicated herein, what is described in this section is not prior art to the description in this application and is not admitted to be prior art by inclusion in this section.
Power converters, especially switch-mode power converters, normally require switching of field effect transistors (FETs) to perform voltage conversion. The switching of FETs is controlled by gate signals of the FETs, which are generated from gate timing signal. Depending on topology, a power converter may need two or more gate signals so that the converter can work. The existing products normally provide only two gate signals from a single input signal, which is typically a pulse-width modulation (PWM) clock signal. Some of the existing products use an external voltage source, R (resistance) and C (capacitance), and an on-chip window comparator to control the timing of the gate signals. These methods have insufficient number of gate signals or have insufficient programmability or both.